I hereby propose to accept Pull Request https://github.com/mimblewimble/grin/pull/2714
which preserves the planned phase out of C31 but puts all later phase outs, of C32 and beyond, on hold, and to replace the term “foreseeable future” in our primary PoW commitment at https://www.grin-forum.org/t/cuckatoo31-im-mutability by the more specific term “next 18 months”.
[20190625 UPDATE] The proposal was accepted in today’s dev meeting.
The graph size upgrades were introduced in https://www.grin-forum.org/t/scheduled-pow-upgrades-proposal as a means to resist single chip ASICs, which were deemed “not meaningfully different from pure computational ones like Bitcoin’s sha256”.
At the time, Grin was planning to use Cuckatoo32+ as its primary PoW. Cuckatoo32 requires 512MB of DRAM and 512MB of SRAM for efficient operation, an amount considered completely infeasible to put on a single chip at that time.
A while later, as argued for in https://www.grin-forum.org/t/cuckatoo32-feasibility, the primary PoW was downsized to Cuckatoo31+. It was thought that even if putting the required 256 MB DRAM + 256 MB SRAM on a single C31 chip was feasible, it would make little economic sense, with the expected poor yield and limited window for ROI.
All this was heavily put into doubt when Obelisk posted details of their GRN1 miner in https://www.grin-forum.org/t/obelisk-grn1-chip-details revealing simulation data of a single chip C31 ASIC as well as planned single chip ASICs for C32, C33, and C34. David Vorick also provided interesting data on expected heat density, showing that such chips run significantly cooler than computation focussed ones.
We need to re-evaluate our future PoW plans in light of
- Single chip Cuckoo ASICs being meaningfully different from computation ones
- the likelihood of single chip ASICs outperforming multi-chip ones for the next 2-8 years
We should wait for both single chip and multi chip ASICs for C31 and/or C32 being produced and compete so we can judge whether yields are reasonable and whether the performance advantage can make up for the higher die costs.
This could lead us to conclude that further phase outs are undesirable.
If we maintain our commitment to the C32 phaseout, and have ASIC manufacturers make significant investments into C33 miners, then we lose the option of freezing the primary PoW at 32 edge bits. Which is a very natural size that’s easier to design circuits for. Also, there’s something nice about the memory requirement being a round 1GB. I’d rather not end up deciding later that single chip ASICs are best after all, but then having them at the less natural 33 bits and more awkward 2GB.